Various techniques for reducing power consumption of a solid-state image pickup device have been proposed.
In PTL 1, for example, reducing power consumption by the following technique is proposed. Pixel synthesis between a signal with long exposure time and a signal with short exposure time is performed a plurality of times, existence of a moving object is decided based on a differential signal between the signal with long exposure time and the signal with short exposure time, and when absence of a moving object is decided, at least some of signal processing circuits are stopped.
Further, in PTL 2, for example, reducing power consumption by the following technique is proposed. When light is incident to a photodiode in a predetermined period after a potential VPD of the photodiode is reset to a predetermined potential VRST, the potential VPD of the photodiode is reduced by an amount corresponding to the amount of the incident light. Thereafter, a falling ramp voltage VRAMP is applied to a source terminal of a metal oxide semiconductor (MOS) transistor which is a source grounding type amplifier for reading the potential VPD of the photodiode. When a voltage difference between a gate and a source of the MOS transistor exceeds a threshold voltage, the MOS transistor is turned on and the output falls rapidly. When a comparator circuit generates a signal having a pulse width from a ramp voltage sweep start point to a rapid fall point of the output of the MOS transistor, the pulse width corresponds to the amount of the incident light. By reading a pixel signal in this way by a pulse width modulation (PWM) system, reducing power consumption is proposed.